1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of programming multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory.
Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. A Flash device is a non-volatile memory comprising an array of cells that can store a pre-determined number of logic xe2x80x9c0xe2x80x9d""s and xe2x80x9c1xe2x80x9d""s. The stored xe2x80x9c1xe2x80x9ds and xe2x80x9c0xe2x80x9ds maintain their state in the absence of external power. These bits can be modified millions of times over the life-time of the device.
An example of a typical configuration for an integrated circuit including a multi-level cell flash memory array 100 and circuitry enabling programming, erasing, and reading for memory cells in the array 100 is shown in FIG. 1. The flash memory array 100 includes individual cells 102. Each cell 102 has a drain connected to a bitline 104, each bitline being connected to a bitline pull up circuit 106 and column decoder 108. The sources of the array cells are connected to Vss, while their gates are each connected by a wordline 109 to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline pull up circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are provided as controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines 104 to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The sense amplifiers 116 further receive voltage reference signals from reference 118. The outputs from sense amplifiers 116 are then provided through data latches or buffers 120 to processor 114.
As mentioned above, the memory array 100 includes multi-level storage cells 102. Multi-level storage refers to the ability of a single memory cell 102 to represent more than a single binary bit of data. A conventional memory cell depicts two states or levels, usually referred to as logic xe2x80x9c0xe2x80x9d and logic xe2x80x9c1xe2x80x9d. A multi-level cell could represent as many as 256 states, or a byte of information.
Multi-level cell storage is obtainable in flash design because a flash memory cell can be programmed to provide multiple threshold voltage (vt) levels. The different vt levels can be sustained over time in a flash memory cell 102, even after repeated accesses to read data from the cell. For example, 16 vt levels stored in a flash memory cell can represent data in four conventional memory cells. Thus, an array of multi-level flash memory cells 102 which can store up to 16 vt levels can provide 4 times the storage capacity of conventional memory cells which only store a binary bit per cell. An example of a multi-level memory array is discussed in U.S. Pat. No. 5,973,958, the entire contents of which are incorporated herein by reference.
Programming of the flash memory array 100 is executed on a word-line basis. The word-line 109 is considered the row address. The word-line will cross multiple bit-lines 104. The bit-line 104 is considered the column address. Each bit-line 104 contains buffer logic to interface to the selected core cell during program, read and erase operations.
FIG. 2 illustrates a selected and unselected bit-line during programming. The unselected bit (bit not to be programmed) is considered inhibited. The bit-line is inhibited from the effects of the program pulse. The selected bit (bit to be programmed) is referred to as uninhibited. This bit will be programmed during the program pulse.
To program a multi-level cell in the flash memory array 100, high gate-to-drain voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming typical gate voltage pulses of 18V are each applied to a cell, while a drain voltage of the cell is set to 3.3V and its source is grounded.
As shown in FIG. 2, the program voltage PVpp of 18V will be applied to the selected word-line (column address). A substantially lesser voltage, such as 10V, will be applied to unselected word-lines. An uninhibited word-line will have a strong field generated across the device. In particular, FIG. 2 shows that with Vss=0V being applied to one end of a bit-line 109 to be uninhibited, the source/drain regions of the bit-line will couple to 0V or ground. This will make the applied field appear much stronger so that effective programming can occur. A high field generated across the memory device will cause electron injection into the floating gate of the selected cell exponentially proportional to strength of the field. This programming procedure results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
Each programmed cell requires a specific amount of applied electric field to obtain the desired programmed vt level. The amount of electric field determines the program speed of a bit-cell. Fast cells will need less applied field while slow cells will need more. The electric field is applied through several program pulses. The use of program pulses allows the device to control program distributions. After each pulse, the cells are program-verified to see if the target vt has been achieved. Using multiple program pulses allows the device to stop programming fast bits while completing the programming the slow bits.
An inhibited word-line will not have a strong field across the device. FIG. 2 shows that with VCC=3.3V being applied at one end of a bit-line 109 to be inhibited, the source/drain regions of bit-line will couple to 8V. This will make the applied field appear much weaker and no effective programming will occur.
As explained above, a multi-level cell 102 utilizes 2N VT levels to represent N logical bits. Standard program times of multi-level cell designs are 2Nxe2x88x921 times that of a single bit program time (SBPT). An example of known programming of two logical bits (N=2) in a single multi-level cell 102 is shown in FIG. 3. In particular, four programming charge distributions A, B, C and E are formed. The centers of the programming charge distributions A-C are preferably positioned between the centers of the charge distributions for the reading pulses. The centers of the charge read distributions are labeled RdA, RdB and RdC corresponding to Read Level A, Read Level B and Read Level C, respectively. RdA typically has a value of approximately 0V, RdB a value of approximately 800 mV and RdC a value of approximately 1.6V. Besides wanting the centers of the program distributions A-C to be positioned between Read Levels A-C, it is desired that there be no intersection between the programming and read distributions so that the read process can accurately predict the levels of the memory cell are properly programmed.
Table 1 is given below that shows a preferred correspondence between the levels A-C and E and the accessed logical bit values Q1, Q2.
Since charge distribution E is the erase state and considered the default setting, there are 2Nxe2x88x921 levels or in the case of N=2 three levels A-C (22xe2x88x921) that must be programmed depending on loaded data. In a known manner of programming, each of the 22xe2x88x921 levels are programmed separately. Each level is programmed separately so that the inhibited and uninhibited bit-lines can be set. This separate programming results in the total programming time being equal to (2Nxe2x88x921) * SBPT (single bit program time). As N, the number of logical bits increases, the programming time becomes exponentially larger and more burdensome. For example, a 4-bit (N=4) multi-level cell design can have a programming time that is 24xe2x88x921 times greater than that of a 2-bit multi-level cell design. Accordingly, there is a need for reducing the programming time for multi-level cells that are programmed for multiple bits.
It should be kept in mind that the cell program speed will vary for a variety of reasons. Bit-cell variations within the population of memory cells due to process issues can cause even neighboring cells to program differently under the same conditions. Program speed can be dependent on the applied voltage. Bit-cells program speed will track VCC, high VCCxe2x80x94faster programming. A bit-cell""s programming characteristics will also change over its own lifetime. A bit-cell will both speed-up and slow-down over the millions of cycles it will encounter. All these factors have a direct effect on the program margins and, thus, need to be controlled.
FIG. 4 illustrates the effect of faster programming on the program vt distribution of FIG. 3. Faster programming generates fewer program pulses since the program distribution""s target windows widen when compared with the program distribution of FIG. 3 represented by dotted pulses. Fewer pulses limit the control on program accuracy since the program margins between consecutive pulses are reduced.
FIG. 5 illustrates the effect of slower programming on the program vt distribution of FIG. 3. Slower programming generates more program pulses since the program distribution""s target windows shrink when compared with the program distribution of FIG. 3 represented by the dotted pulses. The added pulses will improve accuracy. Slower programming affects performance but not program margins or reliability in a multilevel cell design.
FIG. 6 illustrates a target window for high level C for both a fast and slow program distribution window. The point 300 indicates that the minimum program vt for the high level C is not related to program speed but the actual selected program verify level C. The location of point 300 is unaffected by program speed.
As described in U.S. patent application Ser. No. 09/779,864, entitled xe2x80x9cProgram Reconnaissance To Eliminate Variations in VT Distributions Of Multi-Level Cell Flash Memory Designsxe2x80x9d by Allan Parker (Brinks Hofer Case No. 9076/560 and AMD Case No. F0912) filed concurrently with the present application, program reconnaissance for multilevel cells is predicated on the immunity of the highest vt level program speed to effect program margins. By programming the highest vt level in its entirety first, the device can monitor and adjust program speed for successive lower vt states to insure desired accuracy. Regardless of whether the highest vt level programs fast or slow, the device can make the needed adjustments to tune future programming pulses. These actual adjustments are determined through device analysis. This analysis will indicate the program dependence between all levels and specific voltage characteristics. Thus, program reconnaissance is a methodology that allows variations in program distributions to be minimized by continuous adjustments of the program voltage.
While the above-described standard program reconnaissance will compensate for both fast and slow program variations, it requires that the highest vt level be programmed independently of the other vt levels. Removing the highest vt level from the ganged approach of piggyback programming where all levels are programmed as a unit will decrease the program performance.
Please note that in order to achieve the above programming one or more pulses are applied to each vt level separately. In the case of N=2, initially pulses of a voltage, such as 20V, are applied to the highest vt level C. After level C is programmed, one or more pulses of a voltage, such as 19V, are applied to the next lowest level B until level B is programmed. Next, one or more pulses of a lower voltage, such as 18V, are applied to the lowest level C until level C is programmed. Note that the voltages of the pulses are dependent on the desired speed of programming. Note that the highest vt level pulse is adjusted so that the selected bit cells will complete programming in xc2xd the pulse count of the successive vt levels. For example, if the pulse target is 10, the high vt level bits will be targeted for completion of programming in 5 pulses. If the high vt level programming speed increases (fewer pulses), the program voltage can be adjusted to slow successive level programming and insure proper distributions for the lower vt levels.
To erase a cell in the flash memory array 100, the programming process described above is reversed. In the case of N=2, the highest level vt level C is erased by applying pulses of 20V to the substrate while the gate is grounded.
To read the state of a cell, a typical control gate voltage of Rd levels is applied to the cell. The current output from the cell being read is received at an input of a number of the sense amplifiers 116 connected to the same bitline as the cell being read. A second input to each sense amplifier is provided from the reference 118. The reference 118 provides a different reference current to each sense amplifier connected to a bit line, with a current level set equal to current expected from a cell being read when programmed to a desired threshold voltage state. Binary outputs of the sense amplifiers 116 indicate if the cell being read is in a state that is greater than or less than the state of the reference signal received. Outputs of the sense amplifiers are provided through data latch/buffers 120 to the processor 114, enabling the processor 114 to determine from the sense amplifier outputs the threshold state of the cell being read.
One aspect of the present invention regards a method of programming a memory cell that has 2N voltage levels where N greater than 1 and represents the number of bits stored within the memory cell. The method includes setting a target number T of piggyback programming pulses for programming each of 2Nxe2x88x921 vt levels of the memory cell, applying T piggyback programming pulses to the memory cell and determining when the highest one of the 2Nxe2x88x921 vt levels is programmed. If it is determined that the highest one of the 2Nxe2x88x921 vt levels is programmed by a number M of piggyback programming pulses that is less than the target number T, then compensating the programming speed of those ones of said T number of piggyback programming pulses subsequent to the Mth piggyback programming pulse.
A second aspect of the present invention regards a method of programming a multi-level cell flash memory array that has individual multi-level memory cells each having 2N voltage levels where N greater than 1 and represents the number of bits stored within the memory cell and wherein each of the individual memory cells includes a drain connected to a bitline, a source connected to a voltage source Vss and a gate connected to a wordline. The method includes setting a target number T of piggyback programming pulses for programming each of 2Nxe2x88x921 vt levels of one of the individual multi-level memory cells and uninhibiting only a bitline corresponding to a voltage level of the one of the individual multi-level memory cells. Applying T piggyback programming pulses to the uninhibited bitline, determining when the highest one of the 2Nxe2x88x921 vt levels is programmed. If it is determined that the highest one of the 2Nxe2x88x921 vt levels is programmed by a number M of piggyback programming pulses that is less than the target number T, then compensating the programming speed of those ones of the T number of piggyback programming pulses subsequent to the Mth piggyback programming pulse.
Each of the above aspects of the present invention provides the advantage of reducing the programming times of a multi-level memory cell and memory array.
Each of the above aspects of the present invention provide the advantage of providing consistent programming distributions while reducing programming times over many device conditions.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.